8-Bit Serial-In Parallel-Out Shift Register in DIP14 package.<\/p>\n
These\u00a0 8-bit\u00a0 shift\u00a0 registers\u00a0 feature\u00a0 gated\u00a0 serial\u00a0 inputs\u00a0 and an\u00a0 asynchronous\u00a0 clear.\u00a0 A\u00a0 low\u00a0 logic\u00a0 level\u00a0 at\u00a0 either\u00a0 input inhibits entry of the new data, and resets the first flip-flop to the\u00a0 low\u00a0 level\u00a0 at\u00a0 the\u00a0 next\u00a0 clock\u00a0 pulse,\u00a0 thus\u00a0 providing\u00a0 complete\u00a0 control\u00a0 over\u00a0 incoming\u00a0 data.\u00a0 A\u00a0 high\u00a0 logic\u00a0 level\u00a0 on either\u00a0 input\u00a0 enables\u00a0 the\u00a0 other\u00a0 input,\u00a0 which\u00a0 will\u00a0 then\u00a0 determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.<\/p>\n